Unless otherwise indicated herein, the materials described herein are not prior art to the claims in the present application and are not admitted to be prior art by inclusion in this section.
Phase-locked loops (PLL) have been applied to many applications ranging from generating clock signals in microprocessors to synthesizing frequencies. In general, a PLL may include a voltage-controlled oscillator (VCO) that generates an output signal with a frequency that is locked onto a frequency of an input signal (a reference signal). To lock the frequency of the output signal with the frequency of the input signal, a PLL may include a phase frequency detector (PFD) configured to compare the phase of the reference signal to the phase of the output signal generated by the oscillator, and to generate a PFD output that is proportional to the phase difference between the phase of the input signal and the phase of the output signal. Through the feedback of the output signal to the PFD, the PLL drives the frequency of the output signal to the frequency of the input signal and matches the phase of the output signal with the phase of the input signal.